Without limiting the scope of the invention, its background is described in connection with integrated circuit packages, as an example.
Heretofore, in this field, integrated circuits have been formed on semiconductor wafers. The wafers are separated into individual chips and the individual chips are then handled and packaged. The packaging process is one of the most critical steps in the integrated circuit fabrication process, both from the point of view of cost and of reliability. Specifically, the packaging cost can easily exceed the cost of the integrated circuit chip and the majority of device failures are packaging related.
The integrated circuit must be packaged in a suitable media that will protect it in subsequent manufacturing steps and from the environment of its intended application. Wire bonding and encapsulation are the two main steps in the packaging process. Wire bonding connects the leads from the chip to the terminals of the package. The terminals allow the integrated circuit package to be connected to other components. Following wire bonding, encapsulation is employed to seal the surfaces from moisture and contamination and to protect the wire bonding and other components from corrosion and mechanical shock.
Conventionally, the packaging of integrated circuits has involved attaching an individual chip to a lead frame, where, following wire bonding and encapsulation, designated parts of the lead frame become the terminals of the package. The packaging of integrated circuits has also involved the placement of chips on a flexible board where, following adhesion of the chip to the surface of the flexible board and wire bonding, an encapsulant is placed over the chip and the adjacent flexible board to seal and protect the chip and other components.
Unfortunately, current methods for encapsulating silicon chips have led to various problems, including cracking between the encapsulation material and the integrated circuit components, as well as high failure rates due to the multi-step nature of the process. Cracking has plagued the industry because of differences in the coefficient of thermal expansion of the different components, for example, between the soldering materials at the different interfaces and between metallic and non-metallic components. Cracking is also frequent between the silicon wafer and the encapsulation materials, usually epoxies, due to the extreme variations in temperature in various environments and between periods of operation and non-operation.
Furthermore, even if the integrated circuit is successfully assembled, current encapsulation technologies limit the design options available for the designer of, for example, motherboards. The designer of motherboards is forced to use the lead configuration designed into the integrated chip module, in particular the position of Pin #1, which often provides the V.sub.cc or ground for the integrated circuit.
Therefore, a need has arisen for an integrated circuit package and a process for producing an integrated circuit package that provides for flexibility in the location of connection leads. More particularly, a need has arisen for an integrated circuit that provides the designer of motherboards flexibility in the routing of current or ground to the integrated circuit. As integrated circuits become increasingly miniaturized, a need has also arisen for shorter circuit routing on motherboards because of the constraints on the thickness of layers, current, and resistance.